Hi,
I'm looking to clarify functionality of the XI150204 module. Even though it is 10us filter am I correct in thinking that the input signal would need to be on for at least the master cycle time (e.g. 2ms) in order for it to be guaranteed detected at the CtrlX Core?
If input signal duration < Ethercat master cycle time then the XI190202 oversampling module is the correct solution?
Thanks