02/26/2025
How-to

SAFEX FSoE communication between two ctrlX CORES

1 Introduction

This How-to describes how FSoE communication between FSoE devices in different EtherCAT networks can be implemented. The SAFEX #1 is the only EtherCAT device below the ctrlX CORE #1 and is configured as the FSoE master.

SAFEX #2 is the only EtherCAT device below the ctrlX CORE #2 and is configured as an FSoE slave.

The mapping of the FSoE data between the CORE #1 and CORE #2 is implemented via Network Variable Lists (NVL). The configuration of the NVL is very simple and can therefore be recommended.

The How-to basically describes the configuration of the NVL in the PLC programs of the CORE #1 and CORE #2. All programs of the CORE #1 and CORE #2 as well as the programs of the SAFEX #1 and SAFEX #2 are available for download.

Configuration of the NVL in the PLC programs

1.1    Configuration PLC-program CORE #2

The SAFEX #2 is configured as FSoE-Slave. In preparation for mapping the FSoE data, a byte array is declared at the output address %QB0.

Image 1 2: SAFEX #2 is FSoE Slave

The configuration of NVL always starts on the sender side. A name (NVL_Core2toCore1) is defined there and the IP address (192.168.1.1) to which data is to be sent is also specified.

Image 1 3: CORE #2 NVL configuration as Sender

In preparation for mapping the FSoE data, a byte array is declared at the input address %IB0. That means this Input Array of CORE #2 should be send to CORE #1.

Image 1 4: FSoE SlaveInput declaration as Byte-array

Image 1 5: Define an Export file NVL_Core2toCore1.gvl

1.2    Configuration PLC-program CORE #1

The SAFEX #1 is configured as FSoE-Master. In preparation for mapping the FSoE data, a byte array is declared at the output address %QB0.

Image 1 6: SAFEX #1 is FSoE Master
Image 1 7: Choose the exported file NVL_Core2toCore1.gvl for import

Image 1 8: After import we see the imported variable FSoE_

Image 1 9: Mapping the NVL FSoE SlaveInput to FSoE MasterOutput
Image 1 10: CORE #1 NVL configuration as Sender

Image 1 11: FSoE MasterInput declaration as Byte-array

Image 1 12: Define an Export file NVL_Core1toCore2.gvl

1.3    Finish configuration PLC-program CORE #2

Image 1 13: Choose the exported file NVL_Core1toCore2.gvl for import

Image 1 14: After import we see the imported variable FSoE_MasterInput

Image 1 15: Mapping the NVL FSoE MasterInput to FSoE SlaveOutput

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